A Digital-to-Analog Converter (DAC) is a circuit that converts discrete digital measures of signal amplitude into a continuous analog electrical equivalent of the encoded signal. The amplitude and frequency are a specified digital number (for example, a 16 bit word) and the step time between words is the sampling rate (for example, 44,100 times per second). This process can be seen as a mathematical zero-order-hold approximation, wherein tops of bars having fixed width and discrete height (digital amplitudes at a fixed sample rate) are used to approximate continuous analog signals. In such a system, the number of discrete heights defines the DAC's resolution, and the width of each bar is determined by the DAC sampling rate. The goal of the DAC is to adjust the top of each discrete bar to coincide with the level specified by the digital word. Some techniques used to accomplish this include: binary, unary, and delta sigma, and each has its own limitations and requirements.
In binary weighting, individual DAC cells take on discrete amplitudes that increase by multiples of two. The weightings are such that any signal height within the DAC range can be achieved by summing DAC cells to yield the desired amplitude. For example, an amplitude of five would be constructed from a cell of amplitude one and a cell of amplitude four. The accuracy of this method depends on the ability of each cell to match its particular multiple-of-two value.
In unary weighting, each DAC cell takes on the same amplitude. By summing enough cells, any amplitude, up to the maximum number of DAC cells, can be achieved. To reach an amplitude of five, five cells of weight one must be summed. While unary weighting is generally more accurate than binary due to the replication of identical cells, the unary method requires many more DAC cells to operate.
Finally, delta sigma DACs generate the desired signal amplitude by using very few (often just one) DAC cells. The cell is operated at dramatically higher speeds than the signal and alternately exceeds or under represents the desired signal. On average and over a large number of samples, the signal is constructed. By tracking the delta sigma error and filtering any high frequency noise, very high accuracy can be achieved. This is especially true because only a small number of unary cells are needed.
In RF-DAC design, both high bandwidth and low noise floor are desired, but it is often difficult to maximize both of these characteristics in a single design. Delta sigma modulators are used to shape quantization noise away from a transmitted signal, thus relaxing the necessary resolution of the DAC through delta sigma modulation, lowering the noise floor in only the output band. The difficulty with such methods is the narrow bandwidth over which the noise can be shaped away. This leads to a low noise floor but also to a reduced bandwidth.
A common example of this is the embedded mixer delta sigma modulator. A low pass delta sigma modulator operates on a baseband signal followed by analog or pseudo-analog up-conversion. The result of this transmitter architecture is a narrow band signal, limited by the low baseband sample rate, and a frequency agile single transmission band limited by the flexibility of the LO. While this may be acceptable for applications having a narrow range of anticipated signal frequencies, it produces designs that are inflexible and poorly suited to operate in varied signal environments. For example, since the waveform and frequency of target signals in an electronic signal intelligence gathering environment may be unknown, delta sigma modulators having a fixed filter configuration are ill suited to the noise reduction task under those circumstances. Additionally inaccuracies are imparted by the pseudo-analog up-conversion as compared to fully digital up-conversion.
Distinct from the embedded mixer methodology is the direct-digital-to-RF approach which uses digital up-conversion in lieu of analog frequency translation. Digital up-conversion has the advantages of being more accurate with respect to in-phase and quadrature (I/Q) phase, higher in bandwidth due to higher sampling frequencies, and more easily parallelizable (creating multiple frequency independent output signals). Unfortunately, the difficulty of this approach lies in the limited range of frequencies capable of being synthesized. Since the modulated RF signal is constructed in the digital domain, the sample rate of the system should be high enough to support accurate representation of the signal. However, common delta sigma modulators, such as the band-pass modulator, have maximum output frequencies of only ¼ of the sample rate. This leads to frequency synthesis at only a fraction of the digital clock. While delta sigma modulators, such as the high pass modulator, would significantly increase the maximum synthesizable frequency, they are not feasible in these designs because of the small offset between the output signal and the first DAC image.
Therefore, there exists a need in the art for a reconfigurable delta sigma DAC, having direct-digital-to-RF synthesis in a high speed low resolution configuration capable of increasing bandwidth and maximum frequency while removing unwanted signal images or aliases.